8 × 8 × 40 Gbps fully integrated silicon photonic network on chip

Large-scale photonic integration circuits (PICs) have been demonstrated on InP [1] and Si [2–5] substrates for data communications. Silicon PICs 3D integrated with electronic integrated circuits promise future high-speed and cost-effective optical interconnects to enable Exascale performance computers and datacenters [5]. For realistic intra-chip and inter-chip optical links, the bandwidth density and total power consumption are major challenges. Consequently, full integration of all photonics components on chip, including high-speed modulators and photodetectors, and especially lasers, is needed for scalable and energy-efficient system topology designs. A library of functional devices has been developed on silicon with the heterogeneous integrationmethod, including ultralow loss waveguides, arrayed waveguide grating (AWG) routers, low threshold distributed feedback (DFB) lasers, highspeed electroabsorption modulators (EAMs), semiconductor optical amplifiers (SOAs), and photodetectors (PDs) on silicon [6,7], enabling a large-scale photonic integration implementation. In this Letter we demonstrate a high-speed heterogeneous integrated circuit on silicon for chip level interconnection and network. A schematic of the photonic circuit is shown in Fig. 1(a). The network-on-chip (NoC) circuit consists of a reconfigurable ringbus network and eight wavelength division multiplexing (WDM) transceiver nodes, with eight-channel high-speed transmitters and receivers in each node. All transceiver nodes connect to the circular bus waveguide through broadband optical switches. Extra ports are linked to waveguide edge couplers for off-chip fiber coupling. In each transceiver node, the WDM transmitter has eight channels with a single-mode DFB laser [8], monitoring photodetector (MPD), and high-speed EAM on each channel. The corresponding WDM receiver includes eight P-I-N type InGaAs PDs. Some of the nodes have optical preamplifiers. 1 × 8 AWGs are used as a multiplexer and demultiplexer (Mux/DeMux) in the transmitter (Tx) and receiver (Rx), respectively, with a fixed 200 GHz channel spacing in the C/L bands. Mach–Zehnder interferometer switches are used in the network architecture, with cascaded 3 dB adiabatic couplers (ACs) for broadband switching of all WDM channels. The ring-bus architecture defines a reconfigurable NoC. Figure 1(b) illustrates three major working modes. A default mode when a node with its optical switch normally OFF, the corresponding transmitter only talks to its local receiver for self-configuration. When two of the switches are in ON status, the eight-channel signals from one transmitter are routed to the WDM receivers at another node, or to optical fiber coupling for off-chip communication. It can also be defined to be a 1 × N broadcasting network with one transmitter andN receivers by partially turning on the switches. This reconfigurable network architecture provides great flexibility for the system design for chip level optical interconnects. The CMOS compatible fabrication of the NoC circuit has two major parts: silicon-on-insulator (SOI) processes—e.g., definition of surface type Bragg grating, silicon waveguide, edge coupler, optical switches, and AWGs with a 4-in. (100 mm) DUV process— and III/V die bonding and III/V processing for active components. Three different III/V epi structures were optimized individually and transferred to designated areas on the SOI wafer for DFB/ SOA, EAM, and PD, respectively. All active and passive components were protected with silicon oxide and polymer before metallization to reduce capacitance and improve the RF performance. More than 400 functional components, including passive and active components, were integrated into a system on the NoC chip. The process yield of passive components was close to 100% with